Home > Seminars > Nanoelectronic Device Research at UNICAMP

Nanoelectronic Device Research at UNICAMP


2/26/2013 at 2:00PM


2/26/2013 at 3:00PM


258 Fitzpatrick Hall


College of Engineering close button

Alan Seabaugh

Alan Seabaugh

VIEW FULL PROFILE Email: aseabaug@nd.edu
Phone: 574-631-4473
Website: http://www.nd.edu/~nano
Office: 230A Cushing Hall
Curriculum Vitae


Department of Electrical Engineering Frank M. Freimann Chair Professor
College of Engineering Frank M. Freimann Chair Professor
Research Interests: What limits density, speed, power, linearity, gain, noise, and efficiency in devices? What new device capabilities can boost electronic system performance?  Current research: tunnel field-effect transistors, atomically-thin transistors, ionic and ferroelectric memory, self ...
Click for more information about Alan
Add to calendar:
iCal vCal
In this talk we will focus on nanoelectronics devices being studied at the Center for Semiconductor Components (CCS) and Faculty of Electrical and Computer Engineering (FEEC) of the State University of Campinas (UNICAMP). A common tool used to fabricate and analyze the devices is a Focused Ion Beam (FIB) system by FEI. This has shown to be a viable tool to fabricate a small number of nanodevices for proof of concept and characterization. The following devices have been fabricated: FinFET, Junctionless FETs and microsensors based on nanotubes; formation of nanocontacts to CNTs and graphene was also studied. SOI FinFET devices were fabricated using FIB system to mille the Si in order to get FinFET width values between 100 and 200 nm. SiO2 was used as gate dielectric and 20 nm thick TiN and 200 nm thick Al were used as metal gate, drain and source electrodes. Drain-source current (Ids) by drain-source voltage (Vds) measurements were carried out to extract the electrical characteristics of these devices. nMOS Junctionless devices were fabricated on Silicon On Insulator (SOI) substrates using gallium (Ga+) FIB system for silicon milling, to define the Si nano wire (NW) active region, and for depositions of SiO2 and Pt layers, to get the gate dielectric and the gate, drain and source electrodes, respectively. Two methods to define the Si NW active region of the Junctionless devices will be discussed, one, with only Ga+ FIB milling, and, two, with optical lithography, Reactive Ion Etching (RIE) and Ga+ FIB milling. Micro-sensors and reactors based on carbon nanotubes decorated by nanoparticles (CNTs/NPs) are described. The devices were developed for studies of gas-solid heterogeneous reactions at high local temperatures. Reactors with volume of 0.1 ml were machined from single Kovar pieces. CNTs were deposited from solutions in DMF over patterned metal electrodes previously fabricated over oxidized Si substrates using ac di-electrophoresis. Before deposition, 1um wide gaps were milled by FIB to separate electrodes, followed by thermal annealing to improve CNT-electrodes electrical contacts. Sputtering was used for CNTs decoration with metal (Ti, Cu) nanoparticles. This allowed fabricating devices based on decorated suspended nanotubes bridging the electrodes to form a chemical resistor configuration. The suspended tubes can be locally heated up to 500 C by applying mA range electric currents (continuous or pulsed) due to Joule effect, strongly enhancing the gas-solid reactions. Formation of electrical and thermal contacts between metal and graphitic surfaces (multi-wall nanotubes or multi-layer graphene flakes) was studied using conventional electrical methods and confocal Raman spectroscopy where the same laser was used for local heating and measurements of resulting temperature. Effect of laser annealing of contacts has been demonstrated. Electrical and thermal boundary resistances between graphitic surfaces and various substrates (metals, oxide) and the effect of annealing on these parameters have been evaluated.

Seminar Speaker:

Jacobus W. Swart

Jacobus W. Swart

State University of Campinas (UNICAMP), Brazil

Jacobus Swart received his B. Engineer and Dr. Engineer Degrees in 1975 and 1981, respectively, from the Polytechnic School of the University of São Paulo, Brazil. He then worked at K. U. Leuven, Belgium (1982-83, postdoc); CTI, Campinas, (1984, head of Process Engineering); LSI-University of São Paulo (1985-88, Assistant Professor); SID Microeletrônica (1986, part time researcher); RTI, USA (1991, Visiting Scientist); and State University of Campinas, since 1988, presently as Full Professor. He served as director of the Center for Semiconductor Components, from 1998 to 2005. From 2007 until 2011 he was on leave from the University to serve as Director of CTI, a national research center. He worked on CCD, nMOS, CMOS and HBT process integration, device characterization and modeling, gettering processes, plasma processes, rapid thermal processes, silicide formation and characterization. His current research activities and interests include CMOS and MEMS devices, process integration, and process modules such as plasma processing, thin gate dielectrics and carbon nanotubes. Dr. Swart has published 60 papers in International Journals and 170 full papers in Proceedings of International Conferences. He has presented about 50 invited and/or tutorial lectures at different conferences, workshops and visits. He has advised 42 Dr. and MSc. degree students. He is ranked as fellow researcher, level 1A (highest), at CNPq and is a Fellow of the São Paulo state Academy of Science. He is a Senior Member of IEEE, member of ECS and SBMicro and has been president of SBMicro (1988-90 and 1998-2000). He is currently the leader of a large research network in Brazil called NAMITEC, and also of the IC-Brazil Program.

Seminar Sponsors: