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High-k Dielectric Gated Quantum-Well Transistors

This research involves investigation of an optimal scalable architecture for compound semiconductor based quantum-well transistors (QWFETs) in the narrow gap CS materials space. Arsenic and antimonide based compound semiconductor based materials are under consideration for possible replacement of the silicon channels in future CMOS transistors. We have a tightly coupled research agenda that is investigating the following : a) design and demonstrate a scalable quantum well transistor architecture which employs self-aligned charge transfer doped source drain extensions, b) demonstration of a planar architecture instead of recessed gate enabled by high quality gate dielectric incorporation and surface charge compensation, c) demonstration of hole transport enhancement using strain engineering to enable a complementary logic solution d) fabrication of deep sub-micron gate length transistors to extract and benchmark source velocity as a function of gate length, short channel effects for sub 0.5V operating voltage range. This study will provide key insight into the feasibility of CS based narrow gap material such as InxGa1-xAs (0.53 < x < 1) and InAs1-ySby (y ≥ 0.2) as a channel material and incubate new ideas to enhance the energy efficiency of complementary logic transistors. This research is funded by the SRC and DARPA under the Materials, Structures and Devices focus center research center (FCRP)

High-k Dielectric Gated Quantum-Well Transistors