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Sub Hundred Millivolt Supply Voltage Logic Architecture

Many emerging nanoscale devices, charge or alternate state variable based, exhibit low transconductance and output resistance under very low operating voltage conditions, making it essential to reconsider device design in conjunction with new logic representation. To circumvent the limited device gain related issues at low voltages, we are exploring a novel interconnectless binary decision diagram (BDD) based logic architecture based on 2 classes of building blocks such as wrapped gate nanowires and split gate nanodots. The proposed architecture produces a) lower device count than conventional Boolean CMOS logic, b) reduces wiring related energy loss, maintains logic functionality under tens of millivolts of supply voltage, and c) operates with ultra-low energy-delay product. All combinational functions can be realized with the nanodot-based BDD approach and sequential logic functions such as latches, shift registers, flipflops can be realized by interfacing with feedback circuits using nanowire transistors. Our ongoing theoretical and experimental research is investigating whether the aggregate can better the projected state of the art for CMOS for the entire range of information processing tasks. This program is supported by a federal government agency.