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Suman Datta

Professor of Electrical Engineering

111K Electrical Engineering West

The Pennsylvania State University
University Park, PA 16802
Telephone (814) 865-0519
Fax (814) 863-5341
E-mail sdatta@engr.psu.edu
Curriculum Vitae (pdf)
Research Web Site

Research Interests

Nanoelectronic device modeling, fabrication, characterization and their circuit applications for future energy efficient and high performance information processing systems; ultra low voltage computing applications for energy autonomous systems; millimeter wave integrated circuits; convergence between life sciences and solid-state technologies.

Brief Biography

Suman Datta is Professor of Electrical Engineering at the Penn State University with a joint appointment in the Penn State Materials Research Institute (MRI). Suman received his Bachelors in Electrical Engineering from the Indian Institute of Technology, Kanpur, India, in 1995 and his Ph.D. in Electrical & Computer Engineering from the University of Cincinnati, USA, in 1999. He is exploring new materials, novel nanofabrication techniques, new classical and non-classical device structures for CMOS "enhancement" as well as for CMOS "replacement" for future energy efficient, high performance and fault-tolerant information processing systems. He is also interested in exploring correlated electron devices harnessing coupled phase transition phenomena in advanced oxide heterostructures.

Recently, his research group successfully integrated an advanced composite high-k gate stack with mixed arsenide-antomnide quantum-well transistors for ultra-low power logic applications, which waspresented at the 2010 International Electron Devices Meeting (IEDM). This work showcased the possibility of a new generation of mixed arsenide-antimonide transistors consuming 10 times lowerenergy that today's state-of-the-art silicon MOSFETs. His group also demonstrated the world's first vertical inter-band tunnel transistor in the compound semiconductor system. The 100 nanometer channel length tunnel transistor was fabricated at the Penn State Nanofabrication facility, and the experimental and modeling results were presented as a late news paper at the 2009 International Electron Device Meeting (IEDM). Tunnel transistor logic is being pursued as an energy efficient alternate transistor architecure in the post CMOS era.

Prior to joining Penn State, he was a Principal Engineer in the Advanced Transistor and Nanotechnology Group at Intel Corporation. Suman is an internationally recognized expert in device modeling, fabrication and characterization specializing in advanced silicon and compound semiconductor based devices for ultra low-power logic and memory applications. He was the Intel device lead in the joint Intel-QinetiQ research team that demonstrated the first enhancement mode and depletion mode indium antimonide based quantum-well transistors operating at room temperature with record power-delay product. This work, presented at the 2005 International Electron Devices Meeting (IEDM), sparked world-wide interest in pursuing heterogeneous integration of high-mobility narrow-gap materials on silicon platform for low-power, high-speed digital logic applications.

Suman reported on the first experimental evidence of the additive effect of metal gate plasmons screening and channel strain engineering in mitigating the remote soft optical phonon induced mobility degradation in high-k/metal-gate CMOS transistors. This work, presented at the 2003 International Electron Devices Meeting (IEDM), provided the first experimental feasibility demonstration of high-performance strained-channel high-k/metal-gate CMOS transistors. He received the 2003 Intel Achievement Award (the highest technical honor at Intel) for "developing the world's first high-K/metal gate CMOS transistors with record-setting performance". High-K/metal gate CMOS transistors are now used in  every Intel microprocessor at the 45nm and 32 nm technology node.

Suman investigated the device physics, particularly the transport properties and the electrostatic robustness, of non-planar, multiple gate transistors called the "Tri-Gate Transistors" for "extreme scalability", and its implications on logic and SRAM circuit design. His contribution was recognized with a 2002 Divisional Recognition Award from the Intel Logic Technology Development Group for "invention and successful demonstration of high performance Tri-gate CMOS transistors". Tri-Gate transistors will be used in Intel micrprocessors starting from the 22nm technology node.

He has published over 100 journal and conference articles till date and holds 130 US patents related to advanced process technologies and transistor architecture. He is a Senior Member of the IEEE Electron Devices Society.